?2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN9612 " Rev. 1.1.7
7
Electrical Characteristics (Continued)
Unless otherwise noted, V
DD
= 12 V, T
J
= -40癈 to +125癈. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Current Sense
V
CS
CS Input Threshold Voltage Limit
0.19
0.21
0.23
V
I
CS
CS Input Current
V
CSX
= 0 V to 1 V
-0.2
0.2
礎
t
CS_DELAY
CS to Output Delay
CS Stepped from 0 V to 5 V
85
100
ns
Zero Current Detection
V
ZCD_IN
Input Voltage Threshold
(5)
V
ZCD
is Falling
-0.1
0
0.1
V
V
ZCD_H
Input High Clamp Voltage
I
ZCD
= 0.5 mA
0.8
1.0
1.2
V
V
ZCD_L
Input Low Clamp Voltage
I
ZCD
= 0.5 mA
-0.7
-0.5
-0.3
V
I
ZCD_SRC
Source Current Capability
(5)
1
mA
I
ZCD_SNK
Sink Current Capability
(5)
10
mA
t
ZCD_DLY
Turn-On Delay
(5)
ZCDx to OUTx
180
ns
Output
I
SINK
OUTx Sink Current
(5)
V
OUTx
= V
DD
/2; C
LOAD
= 0.1 礔
2.0
A
I
SOURCE
OUTx Source Current
(5)
V
OUTx
= V
DD
/2; C
LOAD
= 0.1 礔
1.0
A
t
RISE
Rise Time
C
LOAD
= 1 nF, 10% to 90%
10
25
ns
t
FALL
Fall Time
C
LOAD
= 1 nF, 90% to 10%
5
20
ns
V
O_UVLO
Output Voltage During UVLO
V
DD
= 5 V; I
OUT
= 100 礎
1
V
I
RVS
Reverse Current Withstand
(5)
500
mA
Soft-Start (C
SS
= 0.1 礔)
I
SS_MAX
Maximum Soft-Start Current
V
COMP
< 3.0 V
-7
-5
-3
礎
I
SS_MIN
Minimum Soft-Start Current
(5)
V
COMP
> 4.5 V
-0.40 -0.25 -0.10
礎
Input Brownout Protection
V
IN_BO
Input Brownout Threshold
0.76 0.925
1.10
V
I
VINSNK
V
IN
Sink Current
V
VIN
> 1.1 V
-0.2
0.2
礎
V
VIN
< 0.8 V
1.4
2
2.5
礎
Input-Voltage Feedforward Range
V
FF_UL
V
IN
Feedforward Upper Limit
(5)
3.1
3.7
4.3
V
V
FF_RATIO
V
FF_UL
/ V
IN_BO
(5)
3.6
4.0
4.3
Phase Management
V
PH,DROP
Phase Dropping Threshold
V
COMP
Decreasing, Transition
from 2 to 1 Phase, T
A
= 25癈
0.66
0.73
0.80
V
V
PH,ADD
Phase Adding Threshold
V
COMP
Increasing, Transition
from 1 to 2 Phase, T
A
= 25癈
0.86
0.93
1.00
V
Over-Voltage Protection Using FB Pin Cycle-by-Cycle (Input)
V
OVPNL
Non-Latching OVP Threshold
(+8% above V
OUT_NOMINAL
)
T
A
= 25癈
DRV1=DRV2=0 V
3.15
3.25
3.35
V
V
OVPNL_HYS
OVP Hysteresis
FB Decreasing
0.24
V
Over-Voltage Protection Using OVP Pin Latching (Input)
V
OVPLCH
Latching OVP Threshold (+15%)
DRV1=DRV2=0 V
3.36
3.50
3.65
V
Note:
5. Not tested in production.
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